Design-Reuse

PLDA Announces XpressRICH4-AXI PCIe 4.0 IP, Providing a High Performance and Reliable AXI Bridge for SoC designs

The newest addition to PLDA?s extensive line of advanced PCIe products provides the highest level of PCIe-to-AXI integration, preventing AXI deadlock with ordering rules management, while delivering ...
EDN

Comparing AMBA AHB to AXI Bus using System Modeling

Embedded system designers have a choice of using a shared or point-to-point bus in their designs. This article discusses the construction of an Advanced Microcontroller Bus Architecture (AMBA) ...
EDN

Self-timed interconnect solution supports AXI bus protocol

SAN FRANCISCO — EDA and intellectual property (IP) startup Silistix Ltd. has added support for the on-chip AMBA AXI bus protocol to the company's synthesized self-timed interconnect technology, ...
Design-Reuse

Silistix Self-Timed Interconnect Solution Adds Support for AXI Bus Protocol

Extends Designer Use of Popular AMBA Buses for Asynchronous Interconnect on SoCs SAN JOSE, CA -- July 17, 2006 -- Silistix, a provider of innovative software for on-chip communications solutions, ...
Electronic Design

Understanding FPGA Processor Interconnects

This file type includes high resolution graphics and schematics when applicable. FPGAs are wonderful tools. They consist of a collection of logic cells called lookup tables (LUTs) surrounded by an ...
Semiconductor Engineering

Locking When Emulating Xtensa LX Multi-Core On A Xilinx FPGA

Today’s high-performance computing systems often require the designer to instantiate multiple CPU or DSP cores in their subsystem. However, the performance gained by using multiple CPUs comes with ...