Semiconductor Engineering

Unraveling PCIe 6.0 Loopback And Digital Near-End Loopback Feature

The PCIe specification has given a specific Link Training and Status State Machine (LTSSM) state named Loopback, which is intended for test and fault isolation use. Basically, it gives a mechanism ...
Semiconductor Engineering

High-Speed Manufacturing And In-Field Scan Test Access Via PCI Express For GPIO Limited SoCs

This post addresses the specific hurdle of effective and efficient manufacturing tests for these complex devices. It outlines ...
Hackaday

PCIe For Hackers: Link Anatomy

Last time, we looked over diffpairs, their basics, routing rules and the notorious tolerances of PCIe when it comes to diffpairs. Now, let’s take a look at the exact signals that make PCIe tick, as ...
TweakTown

Cadence teases PCIe 7.0 hitting 128GT/s with optical PCIe connections, successor to CopprLink

Cadence stole the show recently at the PCI-SIG DevCon 2024 event, and in honor of the 32nd anniversary of the PCI-SIG Developer's Conference, Cadence announced a complete PCIe 7.0 IP solution for HPC ...
Electronic Design

Agilent Introduces Solution for PCI Express 3.0 Receiver Characterization

January 29, 2013. Agilent Technologies Inc. at DesignCon announced an enhanced solution for PCI Express 3.0 receiver characterization. The Agilent PCIe 3.0 receiver characterization solution provides ...