EDN

Reversing the SoC Design Process

It is obvious that IP-based system-on-chip (SoC) design or at least some form of “reuse methodology” is the way to address increasingly complex designs in shrinking time-to-market windows. But with ...
Nasdaq

Cadence Advances Hyperscale SoC Design with Expanded IP Portfolio for TSMC N3E Process Featuring Next-Generation 224G-LR SerDes IP

Proven interface IP architectures realized significant gains in performance and power efficiency on the TSMC N3E process 224G-LR SerDes PHY IP on the TSMC N3E process has achieved first-pass silicon ...
EDN

Design planning for large SoC implementation at 40nm: Guaranteeing predictable schedule and first-pass silicon success

The physical design implementation of large complex deep sub-micron technologies has evolved to a stage where it is essential to consider every aspect of SoC design and implementation during the ...
Business Wire

Cadence Collaborates With Samsung Foundry to Accelerate Hyperscale Computing SoC Design for Process Nodes Down to 4nm

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it has optimized the Cadence ® digital 20.1 full flow for Samsung Foundry’s advanced-process ...
Design-Reuse

Synopsys and SMIC Team to Deliver Proven SoC Design Solution for 65-nm to 40-nm Process Nodes

MOUNTAIN VIEW, Calif. and SHANGHAI, Nov. 15, 2010 -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, and Semiconductor ...
Semiconductor Engineering

Why SoC Designers Need Purpose-Built Semiconductor IP Catalog Tools

Semiconductor intellectual property (IP) management, reuse, and change tracking are essential for efficiently creating chip designs based on proven building blocks, reducing your time-to-market, and ...
Electronic Design

Interview: Harry Luan Addresses SoC Design Challenges

Harry Luan, Kilopass’ chief technology officer and vice president of R&D, has been a key member of the Kilopass team since its inception in 2002. He is an expert in CMOS/non-volatile memory (NVM) ...
SDxCentral

Synopsys 5G SoC enhances 5G development with new RF design flow for TSMC N6RF process

RFICs (Radio Frequency Integrated Circuits) for wireless data transmission systems, such as transceivers and RF front-end components, are becoming more complex based on the demands of our connected ...
Embedded

How virtual prototypes aid SoC hardware design

The world of the hardware design engineer has changed dramatically in recent years. Designers no longer sit and code RTL in isolation to meet a paper specification, and then wait for a hardware ...
Design News

EDA Analytics Tool Boosts SoC Design Productivity

Circuit design involves evaluating a number of design scenarios using available data. To deal with the data explosion associated with increasing design complexity, EDA company Synopsys, Inc. has ...
Design-Reuse

Do SoC Architects Have to Get Physical?

With the rapid adoption of the 16/14nm FinFET semiconductor manufacturing processes, the SoC architect’s job is becoming more difficult. Traditionally, architects were responsible for key decisions ...
Nasdaq

Cadence Collaborates With Samsung Foundry to Accelerate Hyperscale Computing SoC Design for Process Nodes Down to 4nm

Cadence 20.1 digital full flow tuned for Samsung Foundry advanced-process nodes, enabling optimal PPA and first-pass silicon success HPC reference flows based on iSpatial technology enable rapid ...