EDN

ASIC design flow gives CPU core custom performance

The ever-increasing levels of CPU performance demanded by embedded applications and product design cycles that have often been reduced to only a few months, have made it important to produce ...
EDN

Altera’s Structured ASIC design flow now ITAR-compliant for military apps

Altera Corporation has announced that the U.S. Department of State has certified that the company's HardCopy II structured ASIC design and manufacturing flow is compliant with International Trade in ...
Design-Reuse

Domino Logic in ASIC Design Flow - Detailed Methodology and Breakthroughs in High Speed Design Automation Approach

Geneva -- September 22,2008 - Engineers at STMicroelectronic have revealed how to use domino logic, a very fast circuit design style utilized in the highest performance custom designs,in an automated ...
Semiconductor Engineering

In-Design Rail Analysis Is A Beautiful Thing

As a long time designer, ASIC flows amaze me and making them better is my goal. Although a very complex and intricate process, each part of the ASIC flow abstracts the complexity underneath it to ...
Design-Reuse

Altera's Structured ASIC Design Flow Now ITAR-Compliant for Military Applications

SAN JOSE, Calif. -- March 12 2007--Altera Corporation (Nasdaq: ALTR) today announced that the U.S. Department of State has certified that the company's HardCopy(R) II structured ASIC design and ...