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IEEE

A 7-bit 1.75-GS/s 6.9-fJ/conv.-step FoMw Loop-Unrolled Fully Asynchronous SAR ADC in 3-nm CMOS for a 224-Gb/s SerDes Receiver

Abstract: This article presents a 1.75-GS/s single-channel 7-bit successive approximation register (SAR) analog-to-digital converter (ADC) that is based on loop-unrolled architecture with ...